A popular CMOS pixel used in scientific imagers is a so-called 5T (i.e., a 5 transistor) pinned-photodiode pixel (herein after a “5TPPD pixel”). FIG. 1 depicts a schematic view of a conventional NMOS 5TPPD pixel 100. The 5TPPD pixel 100 includes a pinned-photo diode (PPD) 102 as a photosensitive element for photo generating and collecting electrical charge. The PPD 102 is flanked by transfer gate-1 (TG1) 104 and transfer gate-2 (TG2) 106. A sense node 108 is located proximate the TG1 104 and converts charge to a voltage. The sense node 108 is coupled to three ‘read’ MOSFETs 120, 122, 124. These MOSFETS are known as the reset, source follower and row select transistors, respectively. Collectively, they are responsible for reading a video voltage level on the sense node 108.
More specifically, the PPD 102 comprises a diode 126 (n-doped for a NMOS 5TPPD pixel) formed within p-epitaxial silicon 128. The p-epi silicon 128 resides above a highly doped p-substrate 130. During operation of the pixel the p-epi silicon 128 and substrate 130 are assumed to be at ground potential (i.e., zero volts) or an external negative bias potential. A p-doped pinning layer 132 is formed directly above and aligned with the diode 126. The pinning layer 132 assumes the same potential as the substrate, whereas the doping of the diode 126 sets a potential for the PPD 102. A p-well 134 surrounds the PPD 102, the transfer gates 104 and 106, and the sense node 108. The read MOSFETS 120, 122 and 124 as well as additional support circuitry are formed in the p-well 134.
In operation, charge on the sense node 108 is first removed by the reset MOSFET 120 coupled to the VREF potential 136. During charge collection, TG2 106 is “off” (i.e., decoupling the VREF potential 136 from the diode 126) and the TG1 104 is “off” (i.e., decoupling the sense node 108 from the PPD 102). In some implementations, the gate TG2 106 is not present. As photons interact with the PPD 102, electrons are generated and collected in the diode 126 over the time period of exposure. After exposure, TG1 104 is turned “on” to transfer signal charge from the diode 126 to the sense node 108. The electrons present on the sense node 108 are converted to a voltage (by the capacitance related to the sense node 108). This resultant voltage is buffered by the source follower MOSFET 122 and output as a pixel value when the pixel row is selected by MOSFET 124. Once the pixel value is present at the column video output, the PPD 102 and sense node 108 are reset and the imaging process repeats.
The foregoing describes the structure and operation of an NMOS 5TPPD pixel. For a PMOS 5TPPD pixel, the n and p doping is reversed (p becomes n, and n becomes p), the p-well becomes an n-well and the voltages VREF, VDD are set to 0 volts and the substrate is biased at 3.3 volts. In a PMOS 5TPPD pixel, the carriers are holes rather than electrons.
Although thermally generated dark current is very low for the PPD 102, a significant amount of dark charge originates from the transfer gates 104 and 106 (typically 2-3 orders of magnitude higher than the PPD generated dark current). When attempting to measure extremely low signal levels, e.g., 10 electrons per the exposure and read periods, the level of dark current can obscure the signal level measured. In addition, charge trapping and recombination effects that are very common to transfer gates 104 and 106 can reduce the measured signal level. Prior attempts at improving these issues has impacted the charge transfer efficiency (CTE) of the pixel.
Therefore, there is a need in the art for an improved 5TPPD pixel having low dark current, while maintaining high CTE without trapping and recombination problems.